Regarding to the structure of a semiconductor substrate and a method for manufacturing the same, for instance, in a technology disclosed in Japanese Patent Kokai Publication No. JP-P2002-064178A (Patent Document 1), after a semiconductor device is flip-chip connected to a circuit board, such boards and other circuit boards having through vias formed by filling cavities with a conductor paste are alternately stacked, and solder balls are attached on the bottom board to obtain a semiconductor stacked package.
For instance, in Japanese Patent Kokai Publication No. JP-P2001-332863A (Patent Document 2), Japanese Patent Kokai Publication No. JP-P2001-339165A (Patent Document 3), Japanese Patent Kokai Publication No. JP-P2001-352174A (Patent Document 4), Japanese Patent Kokai Publication No. JP-P2002-084074A (Patent Document 5), Japanese Patent Kokai Publication No. JP-P2002-170840A (Patent Document 6), and Japanese Patent Kokai Publication No. JP-P2002-246504A (Patent Document 7), a through hole is formed on a core substrate, a semiconductor chip is mounted face (the active surface) up inside the hole using an adhesive, and a wiring layer is built up over an electrode terminal. Or, through vias are formed on a core substrate, and wiring layers are built up on both surfaces by a semi-additive method. Or, a semiconductor element is mounted face up on a heat sink made of metal or ceramic, and a wiring layer is built up over an electrode terminal.
For instance, in Japanese Patent Kokai Publication No. JP-P2006-339421A (Patent Document 8), after an insulating layer and a conductor layer are formed on a supporting plate by a build-up method, a semiconductor chip, on which stud bumps made of Au or solder bumps are formed, is connected face down to a conductor wiring of the supporting plate by a so-called flip-chip method via the bumps. Then the semiconductor chip is reinforced by an under-fill, and after the periphery of the connected semiconductor chip is covered with resin, a via, an insulating layer, and a conductor layer are formed by a build-up method.
For instance, in Japanese Patent Kokai Publication No. JP-P2005-236039A (Patent Document 9), patterns for positioning a semiconductor IC are formed and corresponding to the side of the chip on a transfer substrate around an area where a semiconductor IC chip is mounted, using a conductor wiring.    [Patent Document 1]    Japanese Patent Kokai Publication No. JP-P2002-064178A    [Patent Document 2]    Japanese Patent Kokai Publication No. JP-P2001-332863A    [Patent Document 3]    Japanese Patent Kokai Publication No. JP-P2001-339165A    [Patent Document 4]    Japanese Patent Kokai Publication No. JP-P2001-352174A    [Patent Document 5]    Japanese Patent Kokai Publication No. JP-P2002-084074A    [Patent Document 6]    Japanese Patent Kokai Publication No. JP-P2002-170840A    [Patent Document 7]    Japanese Patent Kokai Publication No. JP-P2002-246504A    [Patent Document 8]    Japanese Patent Kokai Publication No. JP-P2006-339421A    [Patent Document 9]    Japanese Patent Kokai Publication No. JP-P2005-236039A